1. Field of the Invention
This invention relates to an environment sensing/control circuit for an electronic subsystem, and more particularly, to a dual-mode circuit for controlling an electronic subsystem and for detecting intermittent errors in such a subsystem.
2. Description of Related Art
Modern electronic systems often comprise subsystems containing various components. Reliable operation of the subsystems is often essential to the operation of the systems in which they operate. For example, an on-line transaction processing (OLTP) computer system may include a data storage subsystem which must be highly reliable in order to minimize the possibility of data loss and system failure ("downtime"). In order to provide the most reliable operation for such subsystems, some systems are designed with processors which are capable of sensing and controlling the environment of the associated subsystems. In this way, the system has positive control over its environment, and can activate redundant or back-up systems if a failure occurs, or indicate the occurrence and location of faults for quick repair and recovery.
FIG. 1 shows a prior art system comprising an electronic subsystem 1, containing a variety of controllable elements, such as disk drives 2, power supplies 3, and fans 4, as well as a number of sensors, such as temperature sensors 5. Other sensors may be placed within the disk drives 2, power supply 3, and fans 4 for indicating the operational state of those components.
A plurality of analog signal lines 10 couple the sensors and controllable elements within the subsystem 1 to an analog controller 11, which contains suitable electronic elements (such as controllable switches to activate and deactivate controllable elements and digital-to-analog converters) for control purposes, and sensing circuits (such as analog-to-digital converters) necessary to process the signals transmitted on the signal lines 10. As shown in FIG. 1, some of the signal lines 10 comprise a single conductor (such as the control lines between each temperature sensor 5 and the analog controller 11), while others actually comprise two conductors, one to carry an activation signal from the analog controller 11 to a controllable element (such as the disk drive 2) and the other to carry a verification signal back to the analog controller 11 as an indication that the controllable element has properly responded to the activation signal.
The analog controller 11 is also configured to directly communicate with digital circuitry. Each control line and each sensing line coupled to the analog controller typically has a corresponding digital signal line 12. Typically, to actuate a controllable element within the subsystem 1, the corresponding digital signal line 12 is set to a logical state. The analog controller 11 provides an analog output in direct response to the logical state of each corresponding digital input. Similarly, the analog controller 11 provides a digital output corresponding to each analog input.
It is possible to couple the digital signal lines 12 directly to a central processing unit (CPU) 13, thereby permitting the CPU 13 to monitor the digital signal outputs of the analog controller 11, and provide digital signal inputs to the analog controller 11. However, to do so would require the CPU to constantly monitor the digital signal line 12. For many applications, this would constitute a waste of processor resources. Accordingly, it has been known to provide an environment sensing/control circuit 14 as an intermediate circuit between the CPU 13 and the analog controller 11. The purpose of the environment sensing/control circuit 14 is to latch control signals from the CPU 13, provide such latched signals as digital inputs to the analog controller 11, sense digital inputs from the analog controller 11, and provide an indication to the CPU 13 of changes in such conditions.
FIG. 2 is a schematic diagram of a prior art environmental sensing/control circuit. The circuit actually comprises two distinct sections, a control section and a sensing section. Both sections are coupled to the CPU 13 by a processor bus 21, which may be a standard bus. The major elements of both sections are individually addressable by the CPU 13 by supplying an address which is decoded (the decoder is not shown, but is conventional) such that individual "enable" lines would be coupled to each such major element. In addition, the major elements of both sections are coupled to data input and output lines on the bus 21 for communication with the CPU 13.
In FIG. 2, the control section comprises a control memory register 22, which may be simply a D-type flip-flop. When the control memory register 22 is addressed by the CPU 13, the CPU 13 can provide a logical "0" or a logical "1" on the bus 21 as the input to the control memory register 22 to be "latched" within the control memory register 22. The output of the control memory register 22 is provided on a control output connection 23, which would be directly coupled over a digital input signal line 12 to the analog controller 11.
For reliability purposes, the control memory register 22 is provided with an addressable driver 22' which permits the output of the control memory register 22 to be coupled back onto the bus 21 so that the CPU 13 can verify that its input to the control memory register 22 was, in fact, latched. This capability is referred to in the art as "read after write" verification.
In use, the CPU 13 would address the control memory register 22 and set a logical "0" or logical "1" into the control memory register 22. If desired, the CPU 13 would then read the output of the control memory register 22 by means of the associated driver 22'. The output of the control memory register 22 is coupled by output connection 23 to the analog controller. For example, if the CPU 13 commanded that a disk drive 2 within the subsystem 1 be powered up, the control section of an environment sensing/control circuit 14 corresponding to the selected disk drive 2 would be addressed by the CPU 13, and the logical value corresponding to "power-up" (e.g., logical "1") would be stored in the corresponding control memory register 22. The output of the control memory register 22 would be converted by the analog controller 11 to a suitable signal to cause power to be provided to the selected disk drive 2.
The sensing section shown in FIG. 2 is somewhat more complex than the control section. Digital condition signals from the analog controller 11 are provided as an input to the sensing section via an environmental condition input connection 24, which is coupled to a sensing driver 25. The CPU 13 can directly monitor the condition signal on connection 24 by selecting an addressable direct input driver 25.
The digital condition signal on input connection 24 is also provided to a two-input exclusive-OR (XOR) gate 26, which functions as a comparator. The other input of the XOR gate 26 is provided by a reference memory register 27, which again may be a D-type flip-flop. The reference memory register 27 has an associated driver 27', to provide a "read after write" verification capability. The input to the reference memory register 27 is provided by the CPU 13. The reference memory register 27 latches its input and provides that value as an input to the XOR gate 26. The output of the XOR gate 26 is coupled to a tri-statable driver 28, which is coupled to the processor bus 21.
In operation, the CPU 13 sets a value in reference memory register 27, the output of which is constantly compared with the condition signal on input connection 24. This configuration permits the CPU 13 to set a reference value in the reference memory register 27, and detect any changes or "exceptions" of the condition signal on input connection 24 from that reference value. For example, if the condition signal on input connection 24 represents a temperature state as monitored by the analog controller 11, and has a value of "0" when the temperature is within normal operating limits and a value of "1" when a corresponding temperature sensor 5 within the subsystem 1 detects an out-of-limit condition, the CPU 13 might latch a logical "0" into the reference memory register 27. The output of the XOR gate 26 would, therefore normally be a "0" when the condition signal on input 24 is also a "0" (indicating normal temperature), and would change to a logical "1" if the condition signal on input connection 24 differs in value from the reference signal stored in reference memory register 27. If, on the other hand, the condition being monitored was "valid voltage level present" in a disk drive 2, the normal condition might be a logical "1" and failure would be a logical "0." In this case, a "1" would be latched into the reference memory register 27.
It should be clear from the description above that every control line to the analog controller 11 and every sensing line from the analog controller 11 requires a dedicated control section or sensing section of the type shown in FIG. 2. Thus, for a plurality of digital signal lines 12, a plurality of circuits of the type shown in FIG. 2 would be required. It is possible for the CPU 13 to be configured so as to poll all of the control and sensing sections of a plurality of environment sensing/control circuits. However, it is known to instead use an interrupt technique to provide a single signal to the CPU 13 to indicate that the CPU 13 needs to determine which of a plurality of environment sensing/control circuits has detected an "exception" to a reference signal. Therefore, a "global" OR gate 29 is provided, coupled to the output of each sensing section XOR gate 26 for the plurality of environmental sensing/control circuits. Thus, whenever any of the sensing sections indicates an exception from a reference state, an interrupt request (IRQ) signal is provided by OR gate 29 to the CPU 13. The CPU 13 may then invoke an interrupt routine designed to address each environmental sensing/control circuit individually to detect which XOR gate 26 indicates an exception to a reference state.
A number of problems exist with the prior art environment sensing/control circuits. A principal problem is that the CPU 13 may not respond to an IRQ signal in a sufficiently timely manner to check all of the individual sensing sections of the environment sensing/control circuits before the condition which caused the interrupt signal to become active returns to its "non-exception" state. This is problematic for at least three reasons. The first is that time can be wasted checking each sensing section to determine which caused the interrupt; processing resources are therefore wasted. The second reason is that an intermittent condition which should have been identified can go undetected, thereby reducing the reliability of the subsystem 1 as a whole. The third reason is that interruptions of the CPU 13 in response to intermittent signals can interfere with other operations which the CPU 13 must perform.
Another problem that can occur with the prior art is that once an exception condition exists within the sensing section of an environment sensing/control circuit, the CPU 13 has no means for controllably deactivating the sensing section. Under certain conditions, the CPU 13 may wish to ignore some exception conditions, while still retaining the ability to monitor other exception conditions. The prior art environment sensing/control circuits provide no means for accomplishing this function.
Yet another problem which exists in the prior art is that the input logic convention of the analog controllers 11 is sometimes not consistent. Some analog controllers require a low voltage level input to indicate a logical "1", while other analog controllers require a high voltage level input to indicate a logical "1." This lack of uniformity makes it more difficult for a programmer to use a uniform polarity convention when writing program code which instructs the CPU 13. A similar problem exists with respect to digital output signals from an analog controller 11.
A further problem of the prior art is that the control section and sensing section of the environment sensing/control circuit each require a dedicated signal line. When implementing such a circuit in an integrated circuit, it may be difficult to predict in advance how many control sections and how many sensing sections are required for a particular application. In addition, economics dictate that an integrated circuit have as few signal pins as possible. Therefore, the prior art is not flexible in providing a good match between the number of control sections and the number of sensing sections required for a variety of applications, while minimizing the number of pins in an integrated circuit implementation.
Therefore, it is desirable to provide an environment sensing/control circuit which has means for (1) detecting intermittent error conditions in order to allow a processor to detect which condition among many has caused an exception, (2) selectively and dynamically permitting control of the input and output polarity convention of the circuit, (3) selectively preventing changes in the environmental conditions from generating an interrupt signal, and (4) providing maximum flexibility in configuring control and sensing sections, while minimizing the number of signal lines or pins required for the circuit.
The present invention provides such an environment sensing/control circuit.